News Article · Jun 25, 2026 at 12:41 PM
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IBM unveils sub-1nm 'nanostack' chip technology, claims 100 billion transistors per chip
Industry #IBM #nanostack #sub-1nm #chip technology #semiconductor #transistor #Moore's Law #Albany #High-NA EUV

IBM unveils sub-1nm 'nanostack' chip technology, claims 100 billion transistors per chip

IBM announced a sub-1nm chip technology using a 3D 'nanostack' transistor architecture, claiming up to 100 billion transistors per chip. The research milestone, achieved at its Albany lab, promises 50% more performance or 70% better energy efficiency over its 2nm node, but commercial production is at least five years out.

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IBM has built what it calls the world's first sub-1nm chip technology, a transistor architecture at the 0.7nm node that uses a three-dimensional stacking design to pack nearly 100 billion transistors onto a fingernail-sized piece of silicon. The company announced the milestone on June 25, 2026, at its Albany research complex in upstate New York.

According to IBM, the new node offers up to 50% more performance or up to 70% better energy efficiency compared to its 2nm chip unveiled in 2021. Those figures are projections from research results, not measurements from a shipping product, and they describe different operating points rather than a single chip achieving both simultaneously.

How nanostack works

The technology rests on a design IBM calls "nanostack," which the company describes as the industry's first three-dimensional, nanosheet-based transistor architecture. Instead of laying transistors out across a flat plane and shrinking the gaps between them, nanostack stacks and staggers them vertically using 3D sequential integration. This approach also lets engineers use different material combinations in each stacked layer, tuning the performance and power of each transistor independently.

  • IBM says nanostack delivers 40% scaling in SRAM, the fast on-chip memory that has resisted shrinking in recent generations and is critical for AI workloads.
  • The company validated the architecture through dielectric bonding in CMOS integration and demonstrated a working CMOS inverter, proving the structure can be physically built and can switch.
  • The work was done at the Albany research complex, which is soon to house a High-NA EUV lithography tool from ASML, the next-generation machine seen as essential to printing circuits this small.
  • IBM credited partners including Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions.
  • The company recently formed Anderon, a standalone quantum foundry, as part of the same bid to keep advanced chipmaking onshore.

What comes next

The caveat is the one that attends every IBM chip announcement. The company sold its manufacturing business to GlobalFoundries in 2014 and now develops technology to be licensed and built by others. So this is a research milestone rather than a product, and IBM puts the path to production at as early as five years out. That is a long runway, and a lot can change across it. For now, IBM has a structure that works in the lab, a roadmap it says buys the industry another decade of scaling, and a node name that is really a statement of intent.

Fact check

  • IBM announced a sub-1nm chip technology at the 0.7nm node on June 25, 2026.

    verified · source

  • The technology packs nearly 100 billion transistors onto a fingernail-sized chip.

    verified · source

  • The new node offers up to 50% more performance or up to 70% better energy efficiency compared to IBM's 2nm node.

    reported · source

  • IBM sold its manufacturing business to GlobalFoundries in 2014 and now licenses its technology.

    verified · source

  • IBM puts the path to production at as early as five years out.

    reported · source

Source reporting (6)

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