AMD Unveils Venice-X CPU with 96 Cores, Helios AI Rack Reference Design for 2027

At its Advancing AI 2026 event, AMD announced the Venice-X CPU, a 96-core processor with 1152 MB of 3D V-Cache and clocks up to 5.15 GHz, scheduled for the second half of 2027. The company also unveiled the Helios AI rack reference design developed in collaboration with Schneider Electric.

The Venice-X CPU matches the core count and cache amount of the current Genoa-X but achieves far higher clock speeds. AMD said the processor will target AI inference and HPC workloads, offering a 28 percent single-thread performance uplift over its predecessor.

Helios Rack Reference Design

The Helios rack is a reference architecture for integrating AMD's Instinct MI455X accelerators, EPYC processors, and networking into a standardized rack that data center operators can adopt. Schneider Electric contributed power distribution, cooling, and monitoring designs. The reference standard is intended to help developers incorporate the Helios rack into AI data centers without custom engineering, reducing deployment timelines.

• The Helios rack supports the MI455X accelerator with CDNA 5 architecture, high-bandwidth memory, and up to 1.5 TB of HBM4 capacity.
• AMD partnered with Cerebras Systems to pair EPYC processors with Cerebras Wafer-Scale Engine solutions for low-latency, high-throughput AI inference within the Helios rack framework.
• AMD also introduced the X100 APU, based on Strix Halo, for physical AI and robotics. It combines Zen 5 CPU cores, RDNA 3.5 GPU cores, and is designed for 24/7 operation with a 10-year embedded lifecycle. The X100 will be offered as a Kria System on Module developer platform.

Competitive Landscape and Timeline

AMD's Venice-X launch in H2 2027 positions it against Intel's future Xeon processors and Nvidia's Grace CPU. The Helios rack directly challenges Nvidia's DGX systems and HGX baseboard designs. By offering reference designs with Schneider, AMD aims to reduce the time and cost for data center operators to deploy AI infrastructure at scale. The reference design includes standardized power and cooling interfaces, making it easier for colocation providers and hyperscalers to accommodate the rack.

The Venice-X and Helios rack are part of a broader AMD strategy to provide a complete AI stack from CPU to accelerator to rack-level integration. With the X100 for edge AI and the Cerebras partnership for wafer-scale inference, AMD is building multiple entry points for AI workloads. The first Helios rack deployments are expected in 2027 alongside the Venice-X availability. AMD also confirmed that the MI455X accelerator will sample to customers in early 2027, with production shipments following later in the year.